The present invention relates generally to a new structure and method for chip burn-in and/or testing and during use in the field. More particularly, the invention encompasses a baseplate that is secured to a delicate chip and a method for such an invention is also disclosed. The inventive baseplate provides an added strength to a complex chip while it is being tested and/or burned-in, and then during normal use the baseplate of this invention is an integrated component of the chip.
Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding increase in overall chip complexities. Chip manufacturers are therefore constantly challenged to improve their products. Whereas significant improvements have been made, such improvements alone are not sufficient to eliminate all the problems that effect both yield and reliability. One way to improve yield is to control process parameters. Another way to improve reliability is to test and/or burn-in every chip either before or after the dicing operation.
Historically many screening techniques have also been employed to improve yield and reliability rates to acceptable levels by culling out many of the problems associated with the manufacturing and/or processing of these semiconductor chips.
Multi-chip Modules (MCMs), particularly those with more expensive chips, require Known Good Die (KGD) for attachment. The KGD concept is well known in the art. These chips are burnt-in and/or tested on a temporary chip carrier. If they survive the burn-in and/or are tested good, they are then sorted using different criteria, such as, the speed, and are then mounted on a fully functional MCM. This way, only good chips are attached for subsequent use.
International Business Machines Corporation, Armonk, N.Y., has a TCA (temporary chip attach) process. Another process used in the industry for chip burn-in uses a very complex multilevel thin film wiring carrier with metal bumps on polyimide against which the pads on the chip are pressed to make contact during burn-in and subsequent electrical test. Both these processes require a separate carrier and additional assembly and removal of the KGDs after burn-in and/or test.
Additionally, these problems are becoming more acute for a number of reasons, such as, for example, the chip size is increasing, which is resulting in more I/O (input/output) pads, and it is becoming very difficult to remove the chip from the temporary carrier, such as, by using the shear removal method. In some cases the industry has experienced loss of KGDs due to chip cracking during the shear step to remove chips from the temporary carrier after burn-in and/or test. Additionally, some chips have failed at the internal poly/metallization levels during the chip removal process after testing and/or burn-in.
Furthermore, the method of the prior art has extra assembly and removal steps which adds to the cost. Additionally, as stated earlier the removal method can damage chips, especially the large chips or chips which have other inherent weaknesses. This invention however resolves these and other similar issues.
To prevent these and other problems, the inventors are attaching such chips to a glass ceramic baseplate which has a matched TCE (thermal coefficient of expansion) to the chip, such as, silicon, and which alleviates the problems associated with the prior art, such as, stress-cracking problems that arise due to TCE mismatch issues.
The invention is a novel structure and method for chip burn-in and/or testing.
Therefore, one purpose of this invention is to secure at least one baseplate to a thin chip.
Another purpose of this invention is to use the inventive baseplate to provide an added strength to a complex chip while it is being tested and/or burned-in.
Still another purpose of this invention is to use the baseplate of this invention as an integrated component of the chip.
Yet another purpose of this invention is to form a KGM (known good module).
Still yet another purpose of the invention is to avoid applying stress to low K, back-end-of-line (BEOL) dielectric material which typically has a modulus which is on the order of magnitude lower than traditional SiO2.
Therefore, in one aspect this invention comprises a method of assembling an electronic component to a substrate, said method comprising the steps of:
(a) forming a subassembly of an electronic component joined to a baseplate;
(b) temporarily joining said subassembly to a test apparatus to test the chip;
(c) removing said subassembly from said test apparatus; and
(d) joining said subassembly to a substrate if said electronic component is good.
In another aspect this invention comprises a KGM (Known Good Module) comprising at least one electronic component secured to at least one baseplate.